System and method for storing data in read-only memory

ABSTRACT

A system for storing data in read-only memory is disclosed that comprises bit level conductors, transistors, and sets of reference level conductors. Each reference level conductor has a reference value. A selected reference level conductor transmits a selected reference value to one of the transistors. The transistor transmits the selected reference value to a selected bit level conductor having a selected bit value. The bit level conductors, the transistors and the reference level conductors store data by encoding data as a combination comprising the selected bit value and the selected reference value. A method for storing data in read-only memory is disclosed. Bit level conductors having bit values, transistors, and sets of reference level conductors having reference values are provided. A selected bit value of a selected bit level conductor and a selected reference value of a selected reference level conductor are selected. Data is encoded by translating the data from a digital form to a combination comprising the selected bit value and the selected reference value. The data is stored by coupling the selected bit level conductor to the selected reference level conductor such that the selected reference level conductor can transmit the selected reference value to the selected bit level conductor.

TECHNICAL FIELD OF THE INVENTION

[0001] This invention relates generally to the field of data storage and more specifically to a system and method for storing data in read-only memory.

BACKGROUND OF THE INVENTION

[0002] The rising use of semiconductors in a variety of implementations has led to the increasing demand for more efficient storage of data. Semiconductors are used in a number of products, including computers, automobiles, and household appliances, and are often used to store an increasingly large amount of data in read-only memory (ROM). Moreover, as computational devices become smaller, the space available for storing data has decreased. Known methods for storing data, however, have not been satisfactory in terms of storage efficiency and ease of production.

[0003] Data is stored in ROM by encoding values using a pattern of connections on a semiconductor. Known approaches for programming connections include via, metal, gate, and moat programming. Via programming uses vias, couplings from one semiconductor layer to another, to establish connections. Although via programming is relatively easy to produce, it yields a low storage density, represented as the number of storage bits per unit area, compared to other known ROM programming techniques in similar semiconductor processes. Metal programming establishes connections using metal layers, and is also relatively easy to do. Metal programming, however, also yields a low storage density compared to other known ROM programming techniques. Gate programming uses transistors to establish connections. This type of programming allows for storage of relatively large amounts of data per unit area, but results in slow storage and retrieval. Moat programming uses moats formed in the substrate of the semiconductor to establish connection and also allows for the storage of a relatively large amount of data. In moat programming, however, the programation of the connections must be established during the earliest stages of semiconductor production. Since a ROM cannot be programmed until after a customer has submitted a programming request, programming a semiconductor in the earliest stages results in a relatively long period from customer request to delivery of the product.

[0004] While these approaches have provided improvements over prior approaches, the challenges in the field of data storage have continued to increase with demands for more and better techniques having greater storing efficiency and production. Therefore, a need has arisen for a new system and method for storing data in read-only memory.

SUMMARY OF THE INVENTION

[0005] In accordance with the present invention, a system and method for storing data in read-only memory are provided that substantially eliminate or reduce the disadvantages and problems associated with previously developed systems and methods.

[0006] According to one embodiment of the present invention a system for storing data in read-only memory is disclosed that comprises bit level conductors, transistors, and sets of reference level conductors. Each reference level conductor has a reference value. A selected reference level conductor transmits a selected reference value to one of the transistors. The transistor transmits the selected reference value to a selected bit level conductor having a selected bit value. The bit level conductors, the transistors and the reference level conductors store data by encoding data as a combination comprising the selected bit value and the selected reference value.

[0007] According to one embodiment of the present invention, a method for storing data in read-only memory is disclosed. Bit level conductors having bit values, transistors, and sets of reference level conductors having reference values are provided. A selected bit value of a selected bit level conductor and a selected reference value of a selected reference level conductor are selected. Data is encoded by translating the data from a digital form to a combination comprising the selected bit value and the selected reference value. The data is stored by coupling the selected bit level conductor to the selected reference level conductor such that the selected reference level conductor can transmit the selected reference value to the selected bit level conductor. The reference value may be transmitted to the bit conductor through a switch, for example, a transistor, in a semiconductor process.

[0008] A technical advantage of the present invention is that it uses up to all available or additional conduction layers, such as metal layers, of a semiconductor process to store data. The use of additional layers results in the storage of a large amount of information in a relatively small area. Another technical advantage of the present invention is that the programming of the semiconductor occurs in the later stages of production. By programming at later stages, the present invention allows for faster production of semiconductors from the time of the customer's programming request. Consequently, the present invention allows for the fast production of semiconductors that are able to store a large amount of information.

[0009] Other technical advantages are readily apparent to one skilled in the art from the following figures, descriptions, and claims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] For a more complete understanding of the present invention and for further features and advantages, reference is now made to the following description, taken in conjunction with the accompanying drawings, in which:

[0011]FIG. 1 is a block diagram of one embodiment of a system that may be used in accordance with the present invention;

[0012]FIG. 2 is a flowchart demonstrating one embodiment of a method that may be used in accordance with the present invention; and

[0013]FIG. 3 is a planar view of an exemplary layout identifying stacks, gates, and lines.

DETAILED DESCRIPTION OF THE DRAWINGS

[0014] An embodiment of the present invention and its advantages are best understood by referring to FIGS. 1-3 of the drawings, like numerals being used for like and corresponding parts of the various drawings.

[0015]FIG. 1 is a block diagram of one embodiment of a system 100 that may be used in accordance with the present invention. In general, system 100 comprises a multi-layer semiconductor having one or more bit lines 102 and 104, one or more reference lines 106 and 108, and one or more transistors 110 and 112, which are all coupled to a substrate 114. Substrate 114 may comprise, for example, silicon or other suitable semiconductive material. While conventional ROM cells can store only one of two possible values, system 100 can store one of many possible values using a combination of one of multiple reference level conductors that may be coupled to one of multiple bit level conductors.

[0016] A via layer may be disposed outwardly from substrate 114. The via layer may comprise, for example, silicon dioxide or other suitable insulating material, and may comprise one or more vias 116 a, 118 a, 120 a, and 122 a comprising a metal such as aluminum or other suitable conductive material. To simplify the drawing, the silicon dioxide is not shown in FIG. 1. A metal layer may be disposed outwardly from the via layer. The metal layer may comprise silicon dioxide or other suitable insulating material, and one or more interconnects 124 a, 126 a, 128 a, 130 a, 132 a, 134 a, and 136 a, comprising a metal such as aluminum or other suitable conductive material. To simplify the drawing, the silicon dioxide is not shown in FIG. 1. Additional via and metal layers may be disposed outwardly, in an alternating manner, from the layers disposed proximate substrate 114. Interconnects and vias may form via stacks, for example, vias 120 a-d and interconnects 130 a-d form a via stack.

[0017] Bit line 102 comprises vias 116 a-d and interconnects 124 a-d. Vias 116 a-d and interconnects 124 a-d are coupled to each other in an alternating manner, as shown. Similarly, bit line 104 comprises vias 118 a-d and interconnects 126 a-d coupled to each other in an alternating manner, as shown. Bit level conductors 128 a-d are coupled to a decoding circuit 180 by a bit line 140 and a bit line bus 141. Reference lines 106 and 108 comprise vias and interconnects coupled together in an alternating manner. Reference line 106 comprises vias 120 a-d and interconnects 130 a-d, and reference line 108 comprises vias 122 a-d and interconnects 132 a-d. Reference level conductor sets 142 and 144 comprise interconnects, or reference level conductors. Reference level conductor set 142 comprises reference level conductors 134 a-d, and reference level conductor set 144 comprises reference level conductors 136 a-d.

[0018] Transistors 110 and 112 are formed in an outer surface of substrate 114, as shown. Transistor 110 comprises a source region 150 and a drain region 152 formed in substrate 114. Source 150 and drain 152 may comprise, for example, a doped region of substrate 114, which may itself comprise a suitable semiconductor such as silicon, germanium, gallium arsenide, or other suitable material. Transistor 110 also comprises a gate 154 and a gate oxide layer 156 separating substrate 114 from gate 154. Gate 154 may comprise, for example, a doped polysilicon or other suitable conductive material, and oxide 156 may comprise silicon dioxide or other suitable material. Gate 154 controls the current flowing from source 150 to drain 152. System 100 also comprises a word line 158 coupled to gate 154, which is used to activate gate 154. Transistor 112 may be constructed in a similar manner as transistor 110. Transistor 112 may comprise a drain 162 and a source 160 formed in substrate 114. Transistor 112 may also comprise a gate 164, a gate oxide layer 166, and word line 158 formed and coupled as shown. Transistor 112 may comprise materials similar to those of transistor 110, or may comprise other suitable materials.

[0019] Reference line 106 is coupled to source 150 of transistor 110, and bit line 102 is coupled to drain 152 of transistor 110. Bit line 104 is coupled to drain 162 of transistor 112, and reference line 108 is coupled to source 160 of transistor 112.

[0020] To store an input value, system 100 encodes the input value by assigning, or coupling, a reference level conductor to a bit level conductor. That is, the input value is encoded by a combination of: a default or a reference value and a bit value, where the default value represents no coupling. Each of the reference level conductors 134 a-d of reference level conductor set 142 has a unique reference value, for example, reference level conductors 134 a, 134 b, 134 c, and 134 d have voltage values V₁, V₂, V₃, and V₄, respectively. Other types of suitable reference values may be used. For example, each reference level conductor may have a unique current value. Alternatively, each reference level conductor may be associated with uniquely timed pulse of a voltage or current signal during which the reference level is activated relative to a reference time. Similarly, each bit level conductor 128 a-d has a unique bit value, for example, bit level conductors 128 a-d have bit values b₀-b₄, respectively.

[0021] One of the reference level conductors may be assigned to one of the bit level conductors. The system 100 is statically programmed when it is formed to store a value. The value is encoded by coupling a bit level conductor to a reference level conductor. Due to the multiplicity of bit and reference level conductors, a single system 100, acting as a single memory cell does not merely store one of two values as a conventional static cell, but rather can store one of many possible values. In this manner, a single cell constructed as shown can be representative of many data bits instead of the just one data bit per cell, as associated with conventional memory architecture.

[0022] According to the example shown, reference level conductor 134 c with voltage value V₃, is coupled to and conducts voltage V₃ to reference line 106, which in turn transmits voltage V₃ to source 150. Gate 154 conducts voltage V₃ from source 150 to drain 152, which in turn conducts voltage V₃ to bit line 102. According to this embodiment, interconnect 124 b is coupled to bit level conductor 128 b with bit value b₁. Bit line 140 and bit line bus 141 conducts voltage V₃ to decoding circuit 180.

[0023] Bit line bus 141 comprises one line for each bit level conductor 128 a-d, and is coupled to decoding circuit 180. Decoding circuit 180 comprises one analog to digital converter (ADC) for each line associated with a bit level conductor. ADCs 182, 184, 186, and 188 convert voltage values received from the bit level conductors 128 a-d to digital data. ADCs 182-188 are coupled to decoder 190, which receives digital data from the ADCs and translates the data to a digital output.

[0024] Similarly, reference level conductors 136 a, 136 b, 136 c, and 136 d of reference level conductor set 144 may also have unique voltage values V₅, V₆, V₇, and V₈, respectively. Other suitable reference values, for example, current values and timed pulse values, may be used. The voltage values may be distinct from those of reference level conductors 134 a-d of reference level conductor set 142, that is, V_(i)≠V_(j) for i, j=where i≠j.

[0025] One of the reference level conductors may be assigned to one of the bit level conductors. According to this embodiment, reference level conductor 136 a with voltage value V₅ is coupled to and conducts voltage value V₅ to reference line 108. Reference line 108 conducts voltage V₅ to source 160, which in turn conducts voltage V₅ to gate 164. Gate 164 conducts voltage V₅ to drain 162, which conducts the voltage value to bit line 104. According to this embodiment, interconnect 126 c is coupled to and conducts voltage Vs value to bit level conductor 128 c with bit value b₃. The bit level conductor to which bit line 104 is coupled may be different from the bit level conductor to which bit line 102 is coupled. The voltage-bit level combination of voltage V₅ and bit value b₂ is conducted to decoding circuit 180, where it is translated to an equivalent digital code associated with the sensed combination of the voltage and bit values.

[0026]FIG. 2 is a flowchart demonstrating one embodiment of a method that may be used in accordance with the present invention. The method stores data as a combination of a voltage value and a bit value. To store data, one of many reference values may be assigned to one of many bit level values by using a transistor to couple the reference level conductor associated with the reference value to the bit level conductor associated with the bit value.

[0027] Specifically, the method begins at step 202, where reference lines 106 and 108 and reference level conductors 134 a-d and 136 a-d are provided. Reference lines 106 and 108 and reference level conductors 134 a-d and 136 a-d may be part of a multi-layer memory cell architecture such as that described with reference to FIG. 1. Reference line 106 may comprise interconnects 130 a-d and vias 120 a-d coupled together in an alternating manner. Reference line 106 may be coupled to source 150 of transistor 110. Reference level conductor set 142 may comprise reference level conductors 134 a-d, which may comprise the interconnects of metal layers. Similarly, reference line 108 may comprise interconnects 132 a-d and vias 122 a-d coupled together in an alternating manner. Reference line 108 may be coupled to source 160 of transistor 112. Reference level conductor set 144 may comprise reference level conductors 136 a-d.

[0028] At step 204, bit lines 102 and 104 and bit level conductors 128 a-d are provided. Bit line 102 may comprise interconnects 124 a-d and vias 116 a-d, and bit line 104 may comprise interconnects 126 a-d and vias 118 a-d. Bit line 102 may be coupled to drain 152 of transistor 110, and bit line 104 may be coupled to drain 162 of transistor 112. Bit level conductor set 140 may comprise bit level conductors 128 a-d. Bit level conductors 128 a-d may be coupled to only one interconnect from either bit line 102 or 104, or not coupled at all and retain a default value.

[0029] At step 206, transistors 110 and 112 coupling reference lines 106 and 108 to bit lines 102 and 104, respectively, are provided. Transistor 110 is operable to conduct a voltage value from reference line 106 to bit line 102, and transistor 112 is operable to communicate a voltage value from reference line 108 to bit line 104. At step 208, unique reference values are assigned to reference level conductors 134 a-d and 136 a-d. Voltage values V₁-V_(4 are) assigned to reference level conductors 134 a-d, respectively. Voltage values V₅-V₈ are assigned to reference level conductors 136 a-d, respectively. No two reference level conductors are assigned the same reference value, that is, V_(i)≠V_(j), where i,j=1,2, . . . 8 and i≠j. Other suitable reference values may be used, for example, current values or timed pulse values.

[0030] At step 210, a value is encoded by assigning a reference value to a bit value, that is, the value is encoded as a combination of a reference value and a bit value. To describe the types of combinations possible with reference lines 106 and 108, assume that reference lines 106 and 108 have voltage values {V₁, V₂, . . . , V_(N), V_(H)} and {V_(N+1), . . . , V₂N, VH}, respectively, where V_(i)≠V_(j) for all i≠j, and V_(H) is the null value indicating no assignment. Additionally, assume that the bit values are {b₀, b₁, . . . , b_(M−1)}. The combinations may be described as four groups of combinations. Group I includes assignments from reference line 106 to bit levels 128 a-d, that is, one of {V₁, V₂, . . . , V_(N)} is assigned to one of {b₀, b₁, . . . , b_(M−)}, yielding N·M combinations. Group II includes assignments from reference line 108 to bit levels 128 a-d, that is, one of {V_(N+1), . . . , V_(2N)} is assigned to one of {b₀, b₁, . . . , b_(M−1)}, again yielding N·M combinations.

[0031] Group III includes assignments from both references lines 106 and 108 to bit levels 128 a-d. One of {V₁, V₂, . . . , V_(N)} is assigned to one of {b₀, b₁, . . . , b_(M−1)}, and one of {V_(N+1), . . . , V_(2N)} is assigned to one of {b₀, b₁, . . . , b_(M−1)}, excluding the b_(i) to which already reference line 106 is already assigned, yielding N·M[N·(M−1)] combinations. Group IV includes the null assignment, where no value from either reference line 106 or 108 is assigned to a bit level, yielding one combination. The total number of combinations is calculated by summing the number of combinations from the four groups, as shown in Equation (1): $\begin{matrix} \begin{matrix} {{Total} = {{N \cdot {M\left\lbrack {N \cdot \left( {M - 1} \right)} \right\rbrack}} + {N \cdot M} + {N \cdot M} + 1}} \\ {= {{N \cdot {M\left\lbrack {{N \cdot \left( {M - 1} \right)} + 2} \right\rbrack}} + 1}} \end{matrix} & (1) \end{matrix}$

[0032] Since N for reference levels 134 a-d and 136 a-d is four and M for bit levels 128 a-d is four, the total number of combinations is 225.

[0033] The total number of combinations determines the number of bits that can be stored in a dual stacked via ROM cell such as the architecture described with reference to FIG. 1. The total number may be expressed as 2^(q), where q is the number of bits that can be stored. Thus, the number of bits that can be stored is given by the relation expressed in Equation (2):

q=log₂(total number of combinations)=log₂(N·M[N·(M−1)+2]+1)  (2)

[0034] If N=M=4, then seven bits can be stored in the dual stacked via ROM cell. Note that conventional ROM cells can store only one of two values. The number of bits that may be stored for other values of N and M are shown in TABLE 1. TABLE 1 N = M Combinations q_(N) bits 2 17 4 3 73 6 4 225 7 5 551 9 6 1153 10 7 2157 11 8 3713 11 9 5995 12 10 9201 13 11 13553 13

[0035] Multiple reference lines may be coupled to a single bit line, yielding even more possible codes. When using multiple reference lines, current or time-based reference values may be used.

[0036] A dual stacked via ROM cell is estimated to have an area from two to four times the area of a conventional single bit ROM cell. A four-level stacked via ROM cell, however, can store seven bits while a single bit ROM cell can store only one bit. Hence, the area of the array needed to store one bit using the via ROM cell is {fraction (2/7)} to {fraction (4/7)} the area of the array using the conventional single bit ROM cell. There is an overhead associated with generating the reference voltage values and decoding the voltage values to digital values, but this overhead is very small when considering the space saved with an array of thousands to millions of cells.

[0037] To encode values, each value is assigned one of the possible 2^(q) bit combinations. According to this embodiment, the following encoding operation may be used to encode data; other suitable encoding operations, however, may be used. To simplify the encoding operation, assume N=M such that 2^(q)=N·M[N·(M−1)+2]+1=N²(N²−N+2)+1. Also assume that the values to be stored are nonnegative and are expressed in binary q bit code [X_(q−1), X_(q−2), . . . , X₁, X₀]. This encoding operation uses only combinations from Groups II and III; combinations from other groups, however, may be used.

[0038] To begin, define two pairs of indices to program left-hand side reference line 106 and right-hand side reference line 108:

[0039] (i,j) to determine programming for reference line 106, where i refers to a coupling between a reference level conductor and reference line 106, and j refers to a coupling between bit line 102 and a bit level conductor; and

[0040] (h,k) to determine programming for reference line 108, where h refers to a coupling between a bit level conductor and bit line 104, and k refers to a coupling between reference line 108 and a reference level conductor.

[0041] Next, define two integers r and s. Integer r may be defined using Equation (3):

r=N·j+i  (3)

[0042] where ε=member of or belongs to a set of values;

[0043] r ε[0, N²], i ε[0, N−1], and j ε[0, N]; and

[0044] j ε[0, N−1], if bit level conductor bj is coupled to bit line 102;

[0045] j=N, if no bit level conductor is coupled to bit line 102; and

[0046] i ε[0, N−1], if reference level conductor having reference value V_(i+1) is coupled to reference line 106.

[0047] Integer s may be defined using Equation (4):

s=h·N+k  (4)

[0048] where s ε[0, N²−N−1], h ε[0, N−2], and k ε[0, N−1]; and

[0049] j=0, h ε[0, N−2], if bit level conductor b_(h+1) is coupled to bit line 104;

[0050] j>0, h ε[0, j−1], if bit level conductor b_(h) is coupled to bit line 104; and

[0051] j>0, h ε[j, N−2], if bit level conductor b_(h+1) is coupled to bit line 104.

[0052] Next, define the value X to be stored, as expressed in Equation (5):

X=r[N(N−1)]+s  (5)

[0053] The values of i, j, k, and h that satisfy Equation (5) determines the programming of the cell.

[0054] At step 212, the reference level conductors associated with the value to be stored are coupled to reference lines 106 and 108. According to this embodiment, reference level conductor 134 c, with voltage value V₃, is coupled to reference line 106, and reference level conductor 136 a, with voltage value V₅, is coupled to reference line 108. Reference level conductor 134 c may be coupled to interconnect 130 c using metal programming, where a metal layer is used for coupling. Alternatively, reference level conductor 134 c may be coupled to reference line 106 by via programming, where a via is used for coupling, or other suitable method. Similarly, reference level conductor 136 a may be coupled to interconnect 132 a using metal programming, via programming, or other suitable method.

[0055] At step 214, the bit level conductor associated with the value to be stored is coupled to the bit line. In this embodiment, interconnect 124 b is coupled to bit level conductor b₁ and interconnect 126 c is coupled to bit level conductor b₂ using metal programming, via programming, or other suitable method. The coupling methods used to couple the reference level conductors to reference lines and interconnects to bit level conductors need not be the same.

[0056] At step 216, gates 154 and 164 of transistors 110 and 112, respectively, are activated to allow voltage to flow from reference lines 106 and 108 to bit lines 102 and 104, respectively. According to this embodiment, voltage value V₃ is conducted from reference level conductor 134 c through reference line 106, through transistor 110, through bit line 102 to bit level conductor b₁. Voltage V₃ is conducted through bit line bus 141 to decoding circuit 180 and then to ADC 184. Similarly, voltage V₅ is conducted from reference level conductor 136 a through reference line 108, transistor 112, and bit line 104 to bit line bus 141. Voltage V5 is transmitted through bit line bus 141 to decoding circuit 180 and then to ADC 186.

[0057] At step 218, data encoded as a voltage value is decoded to a digital output by translating the voltage distribution on the bit line bus 141 to a digital value. According to this embodiment, the following decoding operation is used to decode data encoded using the encoding operation previously described; other suitable operations, however, may be used. To simplify the explanation, assume that:

V ₁<V₂< . . . <V_(N)<V_(def)<V_(N+1)< . . . <V_(2N)

[0058] where V_(def) is a default voltage indicating an uncoupled bit line. Also, assume that the voltage values are equally spaced between V₁ and V_(2N). A voltage value V conducted on the line of bit line bus 141 from bit level conductor bp is input into the ADC associated with the bit level conductor. According to this embodiment, V₃ is input into ADC 184, and voltage V₅ is input into ADC 186. Each ADC outputs the following values D_(p), L_(p), R_(p), and U_(p), where p is a bit level conductor index, as described by Equations (6) (9):

[0059] Output L_(p) describes whether reference line 106, the left hand side of the ROM, is coupled to one of reference level conductors 134 a-d, and is expressed by Equation (6): $\begin{matrix} {L_{p} = \left\{ \begin{matrix} 1 & {{{if}\quad 0} < V < V_{def}} \\ 0 & {otherwise} \end{matrix} \right.} & (6) \end{matrix}$

[0060] Output R_(p) describes whether reference line 108, the right-hand side of the ROM, is coupled to one of the reference level conductors 136 a-d, and is expressed by Equation (7): $\begin{matrix} {R_{p} = \left\{ \begin{matrix} 1 & {{{if}\quad V} > V_{def}} \\ 0 & {otherwise} \end{matrix} \right.} & (7) \end{matrix}$

[0061] Output D_(p) indicates the reference level conductor of the input voltage V, and is expressed by Equation (8): $\begin{matrix} {D_{p} = \left\{ \begin{matrix} i & {{{{if}\quad V} = V_{i + 1}},{L_{p} = 1},{{{and}\quad R_{p}} = 0}} \\ k & {{{{if}\quad V} = V_{k + 1}},{R_{p} = 0},{{{and}\quad L_{p}} = 1}} \end{matrix} \right.} & (8) \end{matrix}$

[0062] Output U_(p) describes the null value, and is expressed by Equation (9): $\begin{matrix} {U_{p} = \left\{ {{1\quad {if}\quad V} = {V_{def}0\quad {otherwise}}} \right.} & (9) \end{matrix}$

[0063] The outputs of the ADCs 182-188 are then transmitted to decoder 190, which translates the ADC outputs to a final output. According to this embodiment, decoder 190 uses the following operation to decode the voltage values; other suitable operations, however, may be used. Recall that in the encoding operation previously discussed, the stored value X was encoded using the relationship described by Equation (5):

X=r(N(N−1))+s  (5)

[0064] where r=N·j+i and s=h·N+k.

[0065] Decoder 190 calculates the values for h, i, j, and k using Equations (10)-(13): $\begin{matrix} {i = {\sum\limits_{w = 0}^{N}{L_{w}D_{w}}}} & (10) \\ {j = {\sum\limits_{w = 0}^{N}{wL}_{w}}} & (11) \\ {k = {\sum\limits_{w = 0}^{N}{R_{w}D_{w}}}} & (12) \\ {{h = {\sum\limits_{w = 0}^{N}{H_{w}R_{w}}}}{where}{H_{w} = \left\{ \begin{matrix} {p + 1} & {{{if}\quad j} = {{{0\quad {and}\quad V} > {0\quad {or}\quad j}} \in {{\left\lbrack {j,{N - 2}} \right\rbrack \quad {and}\quad V} > 0}}} \\ p & {{{if}\quad j}\quad \in {{\left\lbrack {1,{j - 1}} \right\rbrack \quad {and}\quad V} > 0}} \end{matrix} \right.}} & (13) \end{matrix}$

[0066] Once decoder 190 determines values i, j, k, and h, decoder 190 calculates the stored value X, which it outputs as digital data, and the method terminates.

[0067]FIGS. 3A an 3A are planar views of exemplary layouts identifying stacks, and gates, and lines. FIG. 3A illustrates reference lines 106 and 108 and bit lines 102 and 104. Gates 154 and 164, word line 158, and bit line bus 141 are also illustrated. FIG. 3B illustrates reference lines 106 and 108 and bit lines 102 and 104. Gates 154 and 164, word line 158, and bit line bus 141 are also illustrated.

[0068] A technical advantage of the present invention is that it uses up to all available or additional conductive layers of a semiconductor process to store data. The use of up to all or available or additional layers results in the storage of a large amount of information in a relatively small area. Another technical advantage of the present invention is that the programming of the semiconductor occurs at the later stages of production. By programming at later stages, the present invention allows for faster production of semiconductors from the time of the customer's programming request. Another technical advantage of the present invention is that it enhances the speed of operation by using layers that provide low resistivity connections to the bit level. Consequently, the present invention allows for the fast production of semiconductors that are able to store a large amount of information.

[0069] Although an embodiment of the invention and its advantages are described in detail, a person skilled in the art could make various alternations, additions, and omissions without departing from the spirit and scope of the present invention as defined by the appended claims. 

What is claimed is:
 1. A system for storing data, the system comprising: two or more bit level conductors, each bit level conductor having a bit value; one or more transistors; and one or more reference level conductors, each reference conductor having a reference value, wherein a selected reference level conductor is operable to transmit a selected reference value to one of the transistors, the transistor is operable to transmit the selected reference value to a selected bit level conductor having a selected bit value, and the bit level conductors, the transistors, and the reference level conductors are operable to store data by encoding data as a combination comprising the selected bit value and the selected reference value.
 2. The system of claim 1, wherein no bit level conductor receives reference values from more than one reference level conductor.
 3. The system of claim 1, further comprising two or more layers wherein each layer comprises no more than one bit level conductor.
 4. The system of claim 1, wherein at least one the reference value is a voltage value.
 5. The system of claim 1, wherein at least one the reference value is a current value.
 6. The system of claim 1, wherein at least one the reference value is a timed pulse value.
 7. The system of claim 1, further comprising a via, wherein the selected reference level conductor is operable to transmit the selected reference value to one of the transistors and the transistor is operable to transmit the selected reference value to the selected bit level conductor using the via.
 8. The system of claim 1, further comprising a metal layer, wherein the selected reference level conductor is operable to transmit the selected reference value to one of the transistors and the transistor is operable to transmit the selected reference value to the selected bit level conductor using the metal layer.
 9. The system of claim 1, further comprising: a bit line bus coupled to the bit level conductors; and a decoding circuit coupled to the bit line bus and operable to decode data encoded as the combination of the selected bit value and the selected reference value by translating the combination to a digital output.
 10. The system of claim 1, wherein the transistor comprises a field effect transistor.
 11. The system of claim 1, wherein one of the bit level conductors receives none of the reference values and retains a default value.
 12. A method for storing data, the method comprising: providing two or more bit level conductors, each bit level conductor having a bit value, one or more transistors, and one or more reference level conductors, each reference level conductor having a reference value; selecting a selected bit value of a selected bit level conductor and a selected reference value of a selected reference level conductor; encoding data by translating the data from a digital form to a combination comprising the selected bit value and the selected reference value; storing data by coupling the selected bit level conductor to the selected reference level conductor, wherein the selected reference level conductor is operable to transmit the selected reference value to one of the transistors, and the transistor is operable to transmit the selected reference value to the selected bit level conductor.
 13. The method of claim 12, wherein no bit level conductor receives reference values from more than one reference level conductor.
 14. The method of claim 12, wherein at least one the reference value is a voltage value.
 15. The method of claim 12, wherein at least one the reference value is a current value.
 16. The method of claim 12, wherein at least one the reference value is a timed pulse value.
 17. The method of claim 12, wherein the step of storing comprises transmitting the reference value using a via.
 18. The method of claim 12, wherein the step of storing comprises transmitting the reference value using a metal layer.
 19. The method of claim 12, further comprising transmitting the reference value from the bit level conductor to a decoding circuit using a bit line bus coupled to the bit level conductors and the decoding circuit.
 20. The method of claim 12, further comprising decoding the stored data by translating the combination comprising the selected bit value and the selected reference value to the digital form using a decoding circuit coupled to the bit level conductors.
 21. The method of claim 12, wherein one of the bit level conductors receives none of the reference values and retains a default value.
 22. A system for storing data, the system comprising: a substrate; two or more layers outwardly disposed from the substrate; two or more bit level conductors disposed outwardly from the substrate, wherein each bit level conductor has a bit value and each layer outwardly disposed from the substrate comprises no more than one bit level conductor; one or more field effect transistors disposed outwardly from the substrate; one or more sets of reference level conductors, each set comprising two or more reference level conductors, each reference level having a voltage value; a bit line bus coupled to the bit level conductors; and a decoding circuit coupled to the bit line bus, wherein a selected reference level conductor of one of the sets is operable to transmit a selected voltage value to one of the transistors, the transistor is operable to transmit the selected voltage value to a selected bit level conductor having a selected bit value using a via, no bit level conductor receives voltage values from more than one reference level conductor, and the bit level conductor set, the transistors, and the reference level conductor sets are operable to store data by encoding data as a combination comprising the selected bit value and the selected voltage value, the decoding circuit operable to decode data encoded as the combination of the selected bit value and the selected reference value by translating the combination to a digital output. 